This invention relates to an accessing technique for a memory array and more particularly to such a technique which allows multiport accessing capability without increasing the total access time of the memory array.
One standard method of accessing a memory array is to provide, for each bit location, a dual accessing line such that the binary signal, either a "0" or a "1", is provided on one line of the pair of lines and the compliment is provided on the other line of the pair. Thus, for a given accessing pair of lines, arbitrarily called A, one line would be "A" while the other would be "A".
To write a "1" into a bit location, for example into location A1, line "A" would be high. At this time two transmission gates between the access lines and memory cell A1 would open controlled by a word select decoder. Since the "A" lead has the high signal applied to it, cell A1 is forced to establish a "1" thereat.
For read operations the sequence has a precharging interval when both access lines "A" and "A" are held high. However, at the end of the precharging interval the high signals are removed from both leads, and they remain high due to parasitic capacitance. The transmission gates are then opened between the access lines and the memory cell. Since there is no maintenance of the high signal on either lead, the memory array flip-flop provides signals on leads "A" and "A" representative of the condition of cell A1. Thus, if the cell had a "1" stored thereat, lead "A" would be left high, and lead "A" would be discharged low. The precharging is required because the memory cells have low power loads and are only capable of discharging the access lines.
The precharging and reading intervals are timed with two phases of a clock. This clock and memory array constitute a synchronously read memory system. The write operation also operates synchronously and thus has a precharge interval, but the precharge is overdriven with the input data and the interval is only used for address and data setup.
Situations exist where it is desired to access a single memory array from more than one port. Typically, this would be achieved by using a multiplexer arrangement at the single port access point and the input/output from the memory would be shared between various registers. This arrangement becomes cumbersome for control purposes and could be costly to implement. An even further drawback to such an arrangement occurs when the memory is already being accessed at its maximum speed for a single port. In such a situation, since the accessing time is fixed, the addition of extra ports causes a reduction in accessing capability from any one port. Accordingly, real time memory operation is impossible to guarantee.
This problem has been overcome in the past by arranging two memories and sequencing between memories for alternate operations. For example, in time slot interchange operations, a frame would be read into a first memory during a first cycle. During the next cycle, the frame would read out of the first memory, while a second frame would be read into the second memory. During the next cycle, the third frame would be read into the first memory, while the second frame would be read from the second memory.
Thus, a need exists in the art for a single memory having multiport capability and where multiple accesses may occur during the same memory cycle, which memory operates without complex peripheral control.